Dear All,      

We are conducting Scheduled Drive for ASIC Design Engineers at Infotech Noida office on 9^th May’10 (Sunday).

Venue: Infotech Enterprises Ltd., B-11, Sector—63, NOIDA—201307 (U.P), Phone Nos: 0120-4161000 till 10 (Land mark: in front of FORTIS HOSPITAL)

Please refer your friends /Colleagues  for these requirements. Resumes received till 11am on 6^th May (Thursday) will be considered for this drive. Shortlisted candidates from Delhi region will be called for this drive and the rest will be scheduled interviews at our Hyderabad office at a later date.

Pl. forward suitable resumes to: Praveen.Vemula@infotech-enterprises.com

Pl. find the Job Descriptions for ASIC Design Engineers:Experience:  4 to 10 years of experience in any of the following areas:                   
Qualification: BE/BTech or ME/MTech/MS in EEE/ECE/CSE 

Job Location: Hyderabad.                                                                                               

Position 1: Physical Design: Partitioning, IO ring preparation, Floorplanning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.

Position 2: Implementation: Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.

Position 3: Logic Design:  Microarchitecture, Logic Design, RTL Coding, Logic Synthesis, Expertise on ARM and Cortex processors and designing subsystems around them. C/C++, Verilog/VHDL, System Verilog.

Position 4:  DFT Engineer: Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools. Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing. Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision. Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG. Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug. Programming in Perl, tcl, awk and c/c++.  Experience in DFT with Logic Vision tools is mandatory.

URL: www.infotech-enterprises.com

 Please drop me your updated resumes only if your profile is matching to our open requirements.

Thanks & Regards

Praveen Kumar.Vemula.

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